Recent rapid advancement in semiconductor technology has brought the advent of very large scale integrated (VLSI) as well as ultra large scale integrated (ULSI) circuitries, resulting in integration of more devices into smaller areas on a single semiconductor substrate. In order to further enhance performance of the VLSI and/or ULSI circuitries, ultra-low dielectric constant (ULK) materials, such as porous materials, are being used as inter-layer dielectric (ILD) to further reduce capacitance such as, for example, inter-layer capacitance and/or other parasitic capacitance that may be undesirable to the performance such as speed of the VLSI and/or ULSI circuitries. Interconnect structures made of metal lines or contacts, such as copper (Cu) for example, are usually formed in and around the porous ULK ILD to connect semiconductor devices on the substrate.
An interconnect structure, which may include trenches and vias, may be formed by first creating a pattern of a three-dimensional interconnect structure in the ILD of a porous ULK material. As is known in the art, the structure or pattern may be formed through processes such as lithography and etching, e.g., a reactive ion etching (RIE). Subsequently, a metal element or material may be deposited onto the trenches and/or vias of the formed structure pattern to create metal contact lines. Excess metal being deposited on the surface of the ULK ILD may be removed through a chemical mechanical planarization (CMP) process. On the other hand, it is also known in the art that depositing a Cu barrier metal (liner), such as Ta/TaN, onto a surface of a porous ULK ILD using a conventional surface cleaning process designed or optimized for dense ILD build may cause element of the metal to penetrate or intrude into the porous material of the ULK ILD. This penetration or intrusion of metal element into porous ULK ILD may cause performance degradation of the metal contacts formed thereon and, in a worst case, shorting of the semiconductor devices that the interconnect structure intends to connect.
In addition to the above-described problems, due to high volume fraction of pores, the trench and via sidewalls of the porous ULK dielectrics are prone to significantly greater damage in the sidewalls relative to the dense low-k dielectrics from the conventional cleaning process, e.g., using oxidative plasma ash chemistries. As such, reducing ash chemistries are often used to remove residual photoresist for these levels with porous dielectrics. Even with these reducing ash chemistries, the damage is significant. Consequently, in the integration scheme that utilizes a single or dual hardmask approach to protect the underlying ULK dielectric from damage during lithography rework, a large lateral undercut is caused in the ULK dielectric directly below the hardmask during a wet clean process step post-etch. This undercut presents a challenge for the physical vapor deposition (PVD) of the Cu barrier metal (liner). Further, the feature profile is modified post-wet etch (damage removal) due to uneven nature of the sidewall damage. For example, larger damage is observed toward the top of the opening and reduced damage is observed toward the bottom of the opening leading to tapered trench sidewall profiles, impacting the performance.